This masters thesis is focused on the issue of processor architecture. The ground of this project is a design of a simple processor, which is enriched by modern components in processor architecture such as pipelining, cache memory and branch prediction. The processor has been made in VHDL programming language and was simulated in ModelSim simulation tool.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:412764 |
| Date | January 2007 |
| Creators | Zlatohlávková, Lucie |
| Contributors | Sekanina, Lukáš, Strnadel, Josef |
| Publisher | Vysoké učení technické v Brně. Fakulta informačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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