Reconfigurable computing systems require supports from powerful computer aided design tools to help users developing the interactions between software programs and hardware circuits. The placement and routing support for reconfigurable processing units is also the key to the efficiency of the computing system. In this thesis, we implemented the placement and routing tool for the FMRPU (Fine-grain Multi-context Reconfigurable Processing Unit). The routing resource among the Logic Arrays supports only 8-bit aligned data width, so the routing of the FMRPU can¡¦t completely imitate from the pattern used by LUT-based routing. Thus we proposed an operation-based design model which accepts a data flow graph that describes the operations of the circuit. After compressing the graph, the tool uses Simulated Annealing algorithm with either Maze Route or Center-of-Gravity Route to map the compressed graph into FMRPU. Through the placement and routing tool we implemented, we have successfully mapped several algorithms used in multi-media applications, such as FFT and DCT, into FMRPU.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0822105-161223 |
| Date | 22 August 2005 |
| Creators | Huang, Tzu-che |
| Contributors | none, none, none, none |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0822105-161223 |
| Rights | unrestricted, Copyright information available at source archive |
Page generated in 0.0013 seconds