High-efficiency performance is one of the most important requirements of power
amplifiers (PAs) for wireless applications. However, the design of highly efficient CMOS
PAs for watt-level applications is a challenging task. This dissertation focuses on the
development of the design method for highly efficient CMOS PAs to overcome the
fundamental difficulties presented by CMOS technology.
In this dissertation, the design method and analysis for a high-power and highefficiency
class-E CMOS PA with a fully integrated transformer have been presented.
This work is the first effort to set up a comprehensive design methodology for a fully
integrated class-E CMOS PA including effects of an integrated transformer, which is
very crucial for watt-level power applications. In addition, to improve efficiency of
cascode class-E CMOS PAs, a charging acceleration technique is developed. The method
accelerates a charging speed to turn off the common-gate device in the off-state, thus
reducing the power loss. To demonstrate the proposed cascode class-E PA, a prototype
CMOS PA was implemented in a 0.18-μm CMOS process. Measurements show an
improvement of approximately 6% in the power added efficiency. The proposed cascode
class-E PA structure is suitable for the design of high-efficiency class-E PAs while it
reduces the voltage stress across the device.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/37145 |
| Date | 13 November 2009 |
| Creators | Lee, Ockgoo |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Detected Language | English |
| Type | Dissertation |
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