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Hardware Implementation Of Inverse Transform &amp / Quantization And Deblocking Filter For Low Power H.264 Decoder

Mobile devices such as PDAs and cellular phones became indispensible part of business and entertainment world. There are a number of applications run on these devices and they tend to increase day by day causing devices tend to consume more battery power. H.264/AVC is an emerging video compression standard that is likely to be used widely in multimedia environments. As a mobile application, video compression algorithm of H.264 standard has a complex structure that increase the power demand of realizing hardware. In order to reduce this power demand, power consuming parts of the algorithm like deblocking filter and transform&amp / quantization need to be specifically changed for low power application. A low power deblocking filter and inverse transform/quantization algorithm for H.264/AVC decoder is to be proposed and implemented on FPGA.

Identiferoai:union.ndltd.org:METU/oai:etd.lib.metu.edu.tr:http://etd.lib.metu.edu.tr/upload/12610976/index.pdf
Date01 September 2009
CreatorsOnsay, Onder
ContributorsAkar, Gozde Bozdagi
PublisherMETU
Source SetsMiddle East Technical Univ.
LanguageEnglish
Detected LanguageEnglish
TypeM.S. Thesis
Formattext/pdf
RightsTo liberate the content for public access

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