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Návrh a optimalizace spínaného komparátoru v 250 nm CMOS technologii / Design and parameters optimization of latched comparator in 250 nm CMOS process

This diploma thesis deals with design methods and optimization techniques of dynamic latched comparators. It compares latched and continuous comparators and describes their principle. Then it analyses three popular latched comparator structures with respect to offset, speed and kickback noise. It shows practical comparator design focused on offset precision.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:318180
Date January 2017
CreatorsMatěj, Jan
ContributorsKledrowetz, Vilém, Prokop, Roman
PublisherVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

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