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FPGA Based Binary Heap Implementation: With an Application to Web Based Anomaly Prioritization

This thesis is devoted to the investigation of prioritization mechanism for web based anomaly detection. We propose a hardware realization of parallel binary heap as an application of web based anomaly prioritization. The heap is implemented in pipelined fashion in FPGA platform. The propose design takes O(1) time for all operations by ensuring minimum waiting time between two consecutive operations. We present the various design issues and hardware complexity. We explicitly analyze the design trade-offs of the proposed priority queue implementations.

Identiferoai:union.ndltd.org:GEORGIA/oai:scholarworks.gsu.edu:cs_theses-1082
Date09 May 2015
CreatorsAlam, Md Monjur
PublisherScholarWorks @ Georgia State University
Source SetsGeorgia State University
Detected LanguageEnglish
Typetext
Formatapplication/pdf
SourceComputer Science Theses

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