Fading channel is a communication channel that experiences different interference and fading due to multi-path signal propagation. The fading channel is designed by the finite impulse response filter with the time-varying impulse characteristic. The realisation of this filtr is based on the TDL (Tapped Delay Line) model, which simulate signal delay and signal attenuation in each branch. The aim of this thesis is to create the VHDL design of selected fading channel simulator and its description for hardware implementation into the FPGA.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:218595 |
| Date | January 2010 |
| Creators | Pirochta, Pavel |
| Contributors | Kováč, Michal, Maršálek, Roman |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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