Hon Kwok-Wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaves 89-91). / Abstracts in English and Chinese. / Chapter 1. --- System Architecture --- p.1 / Chapter 1.1 --- Introduction --- p.1 / Chapter 1.2 --- Receiver Architectures --- p.2 / Chapter 1.2.1 --- Superheterodyne Receiver --- p.2 / Chapter 1.2.2 --- Homodyne Receiver --- p.3 / Chapter 1.2.3 --- Image-Reject Receiver --- p.5 / Chapter 1.2.4 --- Low intermediate frequency Receiver --- p.7 / Chapter 1.3 --- Double Intermediate Frequency Receivers --- p.8 / Chapter 1.3.1 --- Introduction --- p.8 / Chapter 1.3.2 --- Background Theory --- p.8 / Chapter 2. --- Receiver Fundamentals --- p.23 / Chapter 2.1 --- Noise model --- p.23 / Chapter 2.1.1 --- Thermal noise of resistors --- p.23 / Chapter 2.1.2 --- Channel noise of transistors --- p.24 / Chapter 2.2 --- Noise Figure --- p.26 / Chapter 2.3 --- Linearity --- p.26 / Chapter 2.3.1 --- 1 -dB Compression point --- p.27 / Chapter 2.3.2 --- Third Intercept point (IP3) --- p.28 / Chapter 2.3.3 --- Dynamic Range (DR) --- p.30 / Chapter 2.3.3.1 --- Spurious-Free Dynamic Range (SFDR) --- p.30 / Chapter 2.3.3.2 --- Blocking Dynamic Range (BDR) --- p.32 / Chapter 3. --- Spiral Inductor --- p.33 / Chapter 3.1 --- Spiral inductor modeling --- p.34 / Chapter 3.2 --- Spiral Inductor model parameters --- p.36 / Chapter 3.3 --- Characteristic of spiral inductor --- p.36 / Chapter 3.4 --- Inductor Design and Optimization --- p.37 / Chapter 4. --- Low Noise Amplifier (LNA) --- p.39 / Chapter 4.1 --- Introduction --- p.39 / Chapter 4.2 --- Common LNA Architectures --- p.39 / Chapter 4.2.1 --- Resistive Termination --- p.39 / Chapter 4.2.2 --- 1/gm Termination --- p.42 / Chapter 4.2.3 --- Shunt-Series Feedback --- p.43 / Chapter 4.2.4 --- Inductive Source Degeneration --- p.43 / Chapter 4.3 --- Full Schematic diagram of the Low Noise Amplifier --- p.45 / Chapter 4.4 --- Full noise analysis of the LNA using inductive source degeneration --- p.46 / Chapter 4.4.1 --- Output noise due to channel noise --- p.46 / Chapter 4.4.1.1 --- Output noise due to i2d --- p.47 / Chapter 4.4.1.2 --- "Output noise due to i2g,u" --- p.47 / Chapter 4.4.1.3 --- "Output noise due to i2g,c and i2d" --- p.49 / Chapter 4.4.2 --- "Output noise due to Rg R,l Rs" --- p.51 / Chapter 4.4.3 --- Noise factor calculation --- p.52 / Chapter 4.4.3.1 --- Rl calculation --- p.52 / Chapter 4.4.3.2 --- Rg calculation --- p.52 / Chapter 4.4.3.3 --- Ql calculation --- p.53 / Chapter 4.4.3.4 --- wT calculation --- p.53 / Chapter 4.4.3.5 --- x calculation --- p.53 / Chapter 4.5 --- Simulation Result of the low noise amplifier (100 finger gate poly) --- p.54 / Chapter 4.5 --- Experimental Result of the low noise amplifier (100 finger gate poly) --- p.56 / Chapter 5. --- Down-conversion Mixer --- p.58 / Chapter 5.1 --- Introduction --- p.58 / Chapter 5.2 --- Gilbert Cell Mixer --- p.59 / Chapter 5.2.1 --- Circuit Description --- p.59 / Chapter 5.2.2 --- Basic Operation --- p.60 / Chapter 5.2.3 --- Simulation Result of the Gilbert Cell Mixer --- p.62 / Chapter 5.3 --- Single-ended to Differential-ended Converter --- p.66 / Chapter 5.3.1 --- Simulation Result of the Single-Ended to Differential-Ended Converter --- p.68 / Chapter 5.4 --- Experimental Result of The Gilbert Cell Mixer --- p.70 / Chapter 5.4.1 --- 1-dB compression point experiment --- p.70 / Chapter 5.4.2 --- IIP3 experimental setup and result --- p.72 / Chapter 5.4.3 --- "Experimental result of 1 -dB compression point, IIP3, conversion gain, SFDR and BDR" --- p.74 / Chapter 5.4.4 --- LO power verse conversion gain --- p.75 / Chapter 5.4.5 --- Intermediate frequency verse conversion gain --- p.77 / Chapter 5.4.6 --- Experimental result of input matching and isolation --- p.78 / Chapter 6. --- Asymmetric Polyphase Network --- p.81 / Chapter 6.1 --- Introduction --- p.81 / Chapter 6.2 --- Performance of the Asymmetric Polyphase Network --- p.81 / Chapter 6.2.1 --- First Building Block --- p.82 / Chapter 6.2.2 --- Second Building Block --- p.83 / Chapter 6.2.3 --- Third Building Block --- p.84 / Chapter 6.2.4 --- Forth Building Block --- p.84 / Chapter 6.3 --- Simulation result of the asymmetric polyphase network --- p.85 / Chapter 6.4 --- Experimental result of the asymmetric polyphase network --- p.86 / Chapter 7. --- Conclusion --- p.87 / Chapter 8. --- Reference --- p.89 / Chapter 9. --- Appendix A --- p.92 / Chapter 10. --- Appendix B --- p.95 / Chapter 11. --- Appendix C --- p.98 / Chapter 12. --- Appendix D --- p.99
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_323086 |
| Date | January 2000 |
| Contributors | Hon, Kwok-Wai., Chinese University of Hong Kong Graduate School. Division of Electronic Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English, Chinese |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, vi, 99 leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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