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New data synchronization & mapping strategies for PACE - VLSI processor architecture

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1. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.283229

Identifer	oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:283229
Date	January 1995
Creators	Xu, Yifan
Publisher	University of Nottingham
Source Sets	Ethos UK
Detected Language	English
Type	Electronic Thesis or Dissertation