The increasing demand for high-capacity and high-speed I/Os is pushing wireline and optical transceivers to a higher aggregate data rate. Multiple lanes of transceivers are monolithically integrated on a single system on chip (SoC), bringing more stringent requirements for the power consumption and area of a single transceiver. Clocking circuits directly determine the transceiver data rate and take a significant portion of the total power consumption. Power-efficient and high-speed data links rely on efficient and high-performance clock generation and distribution.
Multi-phase clock generators (MPCGs) and phase interpolators (PIs) are two essential blocks in the local clock generator in each transceiver lane. MPCGs can generate multi-phase sampling clocks to increase the sampling rate of a fixed frequency, or they can generate multi-phase input clocks for the PIs to perform phase shifting. Their design also affects the schemes for global clock generation and distribution. 8-phase PIs improve the interpolation linearity compared to 4-phase PIs. However, their input 8-phase clock generation either requires power-hungry, multi-phase global clock distribution, or a complicated local 8-phase clock generator. Conventional clocking techniques have encountered the tradeoff of the jitter, power and phase accuracy for multi-phase clock generation. Moreover, 8-phase PIs also meet the linearity and speed bottleneck due to technology limitations.
In this dissertation, we first discuss ring oscillators for multi-phase clock generation. The tradeoff of jitter and phase accuracy in ring oscillators locked by two-phase (0°/180°) injection is presented. This tradeoff is resolved by using a multi-phase injection-locked ring oscillator (MPIL-ROSC) for multi-phase clock generation. A quadrature delay-locked loop (QDLL) provides the coarse but low-jitter multi-phase injection signals to the MPIL-ROSC, and also tunes the MPIL-ROSC's self-oscillation frequency against process-voltage-temperature (PVT) variations. The MPCG is designed for 8-phase clock generation, and drives an 8-phase PI for clock interpolation. A 65-nm prototype chip shows that an MPIL-ROSC can generate low-jitter and highly accurate 8-phase clocks from 5 GHz to 8 GHz under a 1.1-V to 1.3-V supply variation. Moreover, a 7-bit PI driven by the MPIL-ROSC also achieves a peak-to-peak integral nonlinearity (INLpp) less than 1.90 LSB from 5 GHz to 8 GHz.
To further improve the phase interpolation linearity and operation frequency range, a Twin phase interpolator (Twin PI) and a Delta quadrature delay-locked loop (Delta QDLL) are introduced. The phase nonlinearity of a 4-phase, linear-weight PI stems from approximating sinusoidal-weight summation with linear-weight summation. Consequently, the phase deviations are deterministic, sinusoidal, and repeat themselves among different interpolation quadrants. The Twin PI sums up the equalized-amplitude outputs from two, 4-phase PIs with their PI control codes offset by half of the INL "period". The INLs of two PIs have opposite signs to each other, and thus the summation cancels the majority of nonlinearity. The Twin PI achieves very high linearity across a wide operation bandwidth while only needing 4-phase (quadrature) input clocks, which eases the design of its preceding multi-phase clock generator and offers flexibility for global clock generation and distribution scheme. A Delta quadrature delay-locked loop is further proposed for low-jitter and wideband quadrature clock generation from the delay difference of two parallel delay paths with a background analog quadrature tuning loop. A 65-nm prototype chip demonstrates that a Delta QDLL generates quadrature clocks with an accuracy of 0.9° from 3.5 GHz to 11 GHz. The 7-bit Twin PI achieves less-than-1.45-LSB INLpp from 3.5 GHz to 11 GHz. At 7 GHz the INLpp is 0.72 LSB and the integrated fractional spur is as low as -41.7 dBc under -1429ppm clock modulation.
To sum up, the proposed multi-phase injection-locked ring oscillators for multi-phase clock generation, and the combination of Twin phase interpolators and Delta quadrature delay-locked loop break the performance limitation of the state-of-the-art clocking circuits. The block-level innovation also offers opportunities to reconsider the global clocking scheme to save power and circuit area at the system level.
| Identifer | oai:union.ndltd.org:columbia.edu/oai:academiccommons.columbia.edu:10.7916/g3f1-4e71 |
| Date | January 2022 |
| Creators | Wang, Zhaowen |
| Source Sets | Columbia University |
| Language | English |
| Detected Language | English |
| Type | Theses |
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