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Návrh a implementace nástroje pro formální verifikaci systémů specifikovaných jazykem RT logiky / Design and Implementation of a Tool for Formal Verification of Systems Specified in RT-Logic Language

As systems complexity grows, so grows the risk of errors, that's why it's necessary to effectively and reliably repair those errors. With most of real-time systems this statement pays twice, because a single error can cause complete system crash which may result in catastrophe. Formal verification, contrary to other methods, allows reliable system requirements verification.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:236750
Date January 2009
CreatorsFiedor, Jan
ContributorsStraka, Martin, Strnadel, Josef
PublisherVysoké učení technické v Brně. Fakulta informačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

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