In cellular and personal communications services (PCS) systems based on code division multiple access (CDMA), a pilot signal is used on the forward link for synchronization, coherent detection, soft handoff, maintaining orthogonality between base stations, and, in the future, position location. It is critical that the percentage of power allocated to the pilot signal transmitted by each base station be fixed properly to ensure the ability of the CDMA network to support subscriber demand.
This thesis reports on the design and implementation of a prototype receiver for measuring pilot signals in CDMA PCS systems. Since the pseudonoise (PN) signal of the pilot channel is a priori information, the receiver searches for pilot signals by digitally correlating the received signal with this known, locally generated pilot signal. By systematically changing the phase of this locally generated pilot signal, the receiver scans the received signal to identify all possible signs of pilot signal activity. Large values of correlation indicate the presence of a pilot signal at the particular phase of the locally generated pilot signal. The receiver can also detect multipath components of the pilot signal transmitted from a given base station.
One issue associated with this receiver is its ability to keep the signal power within the dynamic range of the analog-to-digital (A/D) converter at its input. This necessitated the design of an automatic gain control (AGC) mechanism, which is digitally implemented in this receiver.
Simulation studies were undertaken to assist in the design and implementation of the pilot signal scanning receiver. These simulations were used to quantify how various non-idealities related to the radio frequency (RF) front-end and A/D converter adversely affect the ability of the digital signal processing algorithms to detect and measure pilot signals.
Because the period of the pilot signal is relatively long, methods were developed to keep the receiver's update period as small as possible without compromising its detection ability. Furthermore, the high sampling rate required strains the ability of the digital logic to produce outputs at a rate commensurate with real-time operation. This thesis presents techniques that allow the pilot signal scanning receiver to achieve real-time operation. These techniques involve the judicious use of partial correlations and windowing the received signal to decrease the transfer rate from the A/D converter to the digital signal processor. This thesis provides a comprehensive discussion of these and other issues associated with the actual hardware implementation of the pilot signal scanning receiver. / Master of Science
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/36682 |
| Date | 04 May 1998 |
| Creators | Blankenship, T. Keith III |
| Contributors | Electrical and Computer Engineering, Rappaport, Theodore S., Brown, Gary S., de Wolf, David A. |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Detected Language | English |
| Type | Thesis |
| Format | application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | thesis.pdf |
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