Approved for Public Release; Distribution is Unlimited / This thesis developed the sample fabrication and experimental design for studying interfacial creep at thin film / Silicon interfaces. The specific interface of study was the crystalline interface created by Positive Vapor deposition of a metallic thin film on a very smooth Silicon substrate. Emphasis was placed on development and refinement of the fabrication techniques necessary to produce test samples that provide valid reproduction of the interfacial stress state in isolation from other stresses inherent in the complete device. Test sample fabrication utilized traditional laboratory methods combined with leading edge methodology in two fabrication steps; namely diffusion bonding of an Silicon substrate / PVD Aluminum thin film / Silicon substrate composite structure and micro-machining Silicon through the use of a TMAH based etchant. In conjunction with the sample development a test platform was designed, fabricated, assembled, and aligned to provide for isolated parametric characterization of the proposed interfacial creep model. The results of this characterization are anticipated to be of significant utility in improving the design for fabrication and reliability of current and next generation microelectronic and microelectro-mechanical devices. / Lieutenant Commander, United States Navy
| Identifer | oai:union.ndltd.org:nps.edu/oai:calhoun.nps.edu:10945/1624 |
| Date | 03 1900 |
| Creators | Thornell, Mark E. |
| Contributors | Dutta, Indranath, Naval Postgraduate School (U.S.)., Mechanical and Astronautical Engineering |
| Publisher | Monterey California. Naval Postgraduate School |
| Source Sets | Naval Postgraduate School |
| Detected Language | English |
| Type | Thesis |
| Format | xiv, 43 p. : ill. ;, application/pdf |
| Rights | This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States. |
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