A novel power-saving and small-area digital output cell is proposed in the first topic of this thesis. The new output cell dramatically reduces the output power consumption by filtering pre-defined spikes, which have been considered as one of the major power dissipation sources of the whole chip, with little sacrifice of speed or delay. The bound of the spikes to be removed can be pre-defined either dynamically by digital selection signals or permanently by fuses to be burned. The maximum operating clock is 200 MHz given a 10 pF off-chip load based on testing result of the testkey chip with an almost 28 % power reduction at all PVT corners.
The second topic presents a design of a 19-T (19 transistors) full adder with high impedance circuit and conflict circuit. The transistor count is dramatically reduced such that the power dissipation as well as the area on chip is very small .
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0106106-001304 |
| Date | 06 January 2006 |
| Creators | Chang, Yuan-Shing |
| Contributors | Chua-chin Wang, Chi-feng Wu, Jih-ching Chiu |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0106106-001304 |
| Rights | not_available, Copyright information available at source archive |
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