The digital product increases widely and vastly. We need a converter to change analog signal to digital one. However, the requirement of analog-to-digital converter is rising due to progress of DSP (Digital Signal Processor). In most ADC structure there have an important building block called the front-end sample-and-hold circuit (SHA) . I will design and implement a high speed and low power sample and hold circuit.
In this thesis, the circuits are designed with UMC 90nm 1P9M CMOS process and 1.2V of supply voltage. The speed and resolution of SHA are 100Ms/s and 10bits individually. The circuit is implemented with class AB amplifier.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0805108-190317 |
| Date | 05 August 2008 |
| Creators | Liu, Tu-tang |
| Contributors | Chia-Hsiung Kao, Ko-Chi Kuo, Shiann-Rong Kuang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805108-190317 |
| Rights | not_available, Copyright information available at source archive |
Page generated in 0.0018 seconds