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Testovací rozhraní integrovaných obvodů s malým počtem vývodů / A Test Interface for Integrated Circuits with the Small Number of Pins

This study explores the possibilities for reducing the number of pins needed for scan mode interface. In the first part of this paper the existing solutions and methods that are usable for this purpose are described. Specific four pin, three pin, two pin, one pin and zero pin interfaces are designed in second part. Advantages and disadvantages of existing solutions and methods as well as designed and proposed interface are summarized in the conclusion.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:320175
Date January 2017
CreatorsTománek, Jakub
ContributorsDvořák, Vojtěch, Šťáva, Martin
PublisherVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

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