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Rozhraní pro průmyslovou HD kameru / Industrial HD camera interface

Master´s thesis deals with creating circuit for receiving data from industrial camera. IP Core is designing for FPGA. Theoretical part of the work describes SDI interface, analysis of relevant SMPTE standards and specification of data format. The thesis include general characteristics of multigigabit transceivers. Practical part include VHDL description of SDI receiver. Thesis presents simulations of created circuit, implementation for real application and measurement results for signal transmission over slip ring.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:221114
Date January 2015
CreatorsJuřica, Libor
ContributorsDvořák, Vojtěch, Bohrn, Marek
PublisherVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

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