Modern superscalar processors exploit instruction-level parallelism (ILP) by
issuing multiple instructions in a single cycle because of increasing demand for higher
performance in computing. However, stalls due to cache misses severely degrade the
performance by disturbing the exploitation of ILP. Multiprocessors also greatly
exacerbate the memory latency problem. In SMPs, contention due to the shared bus
located between the processors's L2 cache and the shared memory adds additional delay
to the memory latency. In distributed shared memory (DSM) systems, the memory
latency problem becomes even more severe because a miss on the local memory requires
access to remote memory. This limits the performance because the processor can not
spend its time on useful work until the reply from the remote memory is received.
There are a number of techniques that effectively reduce the memory latency.
Multithreadings has emerged as one of the most promising and exciting techniques to
tolerate memory latency. This thesis aims to realize a simulator that supports software-controlled
multithreadings environment on a Distributed Shared Memory and to show
preliminary simulation results. / Graduation date: 2000
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/33079 |
| Date | 15 December 1999 |
| Creators | An, Ho Seok |
| Contributors | Lee, Il-Beom |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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