Return to search

A compile-time approach for chaining and execution control in the AN/UYS-2 parallel signal processor

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 1992. / Thesis Advisor: Shukla, Shridhar B. "June, 1992." Description based on title screen as viewed on March 10, 2009. Includes bibliographical references (p. 47). Also available in print.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/313750850
Date January 1992
CreatorsBell, Harold A.
PublisherMonterey, Calif. : Naval Postgraduate School,
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish

Page generated in 0.0028 seconds