The resolution of CMOS image sensor is becoming higher and higher, while for identifying its performance, designers need to do a series of simulations, and this work consumes large CPU time in classical design environment. This thesis titled "Fast Scalable and Variability Aware CMOS Image Sensor Simulation Methodology" is dedicated to explore a new simulation methodology for improving the simulation capability. This simulation methodology is used to study the image sensor performance versus low level design parameter, such as transistor size and process variability. The simulation methodology achieves error less than 0.4% on 3T-APS architecture. The methodology is tested in various pixel architectures, and it is used in simulating image sensor with 15 million pixels, the simulation capability is improved 64 times and time consumption is reduced from days to minutes. The potential application includes simulating array-based circuit, such as memory circuit matrix simulation.
| Identifer | oai:union.ndltd.org:CCSD/oai:tel.archives-ouvertes.fr:tel-01066786 |
| Date | 31 January 2014 |
| Creators | Feng, Zhenfu |
| Publisher | Ecole Centrale de Lyon |
| Source Sets | CCSD theses-EN-ligne, France |
| Language | English |
| Detected Language | English |
| Type | PhD thesis |
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