In this thesis, two FPGA testbeds to demonstrate low-latency deterministic Guaranteed-
Rate (GR) connections in packet switched networks such as the Internet of Things are
developed. Each FPGA testbed consists of multiple simple Input Queued (IQ) switches
or routers, interconnected in a given topology to form a forwarding-plane. Each switch
has an associated switch controller with several programmable Lookup- Tables (LUTs).
A Software Defined Networking (SDN) control plane can configure the switch controllers
to establish the GR connections in the forwarding-plane of IP routers or layer- 2 packet
switches. According to a recent paper in the IEEE Transactions on Networking; (1) The
use of very low jitter GR connections can reduce queuing delays to negligible values, so
that the end-to-end delays can be reduced to the buffer latency. (2) The routers, switches
and links can operate at 100% loads, while simultaneously guaranteeing very low end-
to-end latencies. The goal of the thesis is to evaluate these properties in real hardware
clocked at MegaHertz clock rates. In the first testbed, a network of 8 simple IQ switches
organized in a linear array is synthesized on an Altera Cyclone IV FPGA. 128 GR traffic flows were routed through the testbed to effectively saturate the switches and links. In
the second testbed, a USA backbone topology with 26 simple IQ switches and 88 links
is synthesized on the FPGA. Over 300 GR traffic flows were routed through the USA network to achieve utilizations exceeding 90%. In both testbeds, packets move through the forwarding plane at a clock rate of 65 MHz, transferring millions of packets per second, and statistics are recorded. Both testbeds con rm that traffic flows achieve deterministic GR service with minimum buffering, where end-to-end delays are effectively reduced to the fiber latency. These hardware testbeds demonstrate the technical feasibility of achieving deterministic GR services in a packet-switched network such as Internet of Things using simple FPGA switch controllers working with an SDN control plane. The technology also applies to networks of simple optical packet switches with minimal buffering. / Thesis / Master of Applied Science (MASc)
| Identifer | oai:union.ndltd.org:mcmaster.ca/oai:macsphere.mcmaster.ca:11375/18135 |
| Date | 11 1900 |
| Creators | Rezaee, Maryam |
| Contributors | Szymanski, Ted, Electrical and Computer Engineering |
| Source Sets | McMaster University |
| Language | English |
| Detected Language | English |
| Type | Thesis |
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