Recent years have witnessed the emergence of microprocessors that are
embedded within a plethora of devices used in everyday life. Embedded
architectures are customized through a meticulous and time consuming
design process to satisfy stringent constraints with respect to
performance, area, power, and cost. In embedded systems, the cost of
the memory hierarchy limits its ability to play as central a
role. This is due to stringent constraints that fundamentally limit
the physical size and complexity of the memory system. Ultimately,
application developers and system engineers are charged with the heavy
burden of reducing the memory requirements of an application.
This thesis offers the intriguing possibility that compilers can play
a significant role in the automatic design space exploration and
optimization of embedded memory systems. This insight is founded upon
a new analytical model and novel compiler optimizations that are
specifically designed to increase the synergy between the processor
and the memory system. The analytical models serve to characterize
intrinsic program properties, quantify the impact of compiler
optimizations on the memory systems, and provide deep insight into the
trade-offs that affect memory system design.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/11605 |
| Date | 11 July 2006 |
| Creators | Rabbah, Rodric Michel |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Language | en_US |
| Detected Language | English |
| Type | Dissertation |
| Format | 674645 bytes, application/pdf |
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