This thesis focuses on problem-solution analysis of synchronous digital circuits; the results of which are autosynchronous circuit design methodology, timing parameter definitions based on simulation models and constraint settings. The RTL transformation of the synchronous state machine in VHDL language to an autosynchronous state machine was created with minimal modifications for the simple design of these circuits. Following this, a comparison of the transformed state machines with their synchronous originals in parameters such as chip area, current consumption and timing specification domain is introduced. The summation of this thesis displays a theoretical comparison of several types of synchronization (synchronous, autosynchronous, fundamental asynchronous, EAIC, Bundled-data, Dual-rail) which are presented on the single state machine example with the same technology parameters.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:233515 |
| Date | January 2010 |
| Creators | Kováč, Michal |
| Contributors | Kostka,, František, Jalovecký, Rudolf, Kolouch, Jaromír |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Slovak |
| Detected Language | English |
| Type | info:eu-repo/semantics/doctoralThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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