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Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits / 低電圧集積回路の消費エネルギー最小化のための解析的性能予測とオンチップメモリ構造

京都大学 / 0048 / 新制・課程博士 / 博士(情報学) / 甲第20778号 / 情博第658号 / 新制||情報||113(附属図書館) / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 小野寺 秀俊, 教授 佐藤 高史, 教授 黒橋 禎夫 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

Identiferoai:union.ndltd.org:kyoto-u.ac.jp/oai:repository.kulib.kyoto-u.ac.jp:2433/228252
Date24 November 2017
CreatorsShiomi, Jun
Contributors小野寺, 秀俊, 佐藤, 高史, 黒橋, 禎夫, 塩見, 準, シオミ, ジュン
PublisherKyoto University, 京都大学
Source SetsKyoto University
LanguageEnglish
Detected LanguageEnglish
Typedoctoral thesis, Thesis or Dissertation
Formatapplication/pdf
RightsCited from:, Jun Shiomi, Tohru Ishihara, and Hidetoshi Onodera, “A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation, ” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E100-A, no. 12, pp. (TBD), Dec. 2017 (to appear). (🄫2017 IEICE), Jun Shiomi, Tohru Ishihara, and Hidetoshi Onodera, “Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing, ” Integration, the VLSI Journal, Elsevier, 2017, in press http://dx.doi.org/10.1016/j.vlsi.2017.07.001 (🄫2017 Elsevier), Jun Shiomi, Tohru Ishihara, and Hidetoshi Onodera, “Statistical Timing Modeling Based on a Lognor- mal Distribution Model for Near-Threshold Circuit Optimization, ” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E98-A, no. 07, pp. 1455–1466, Jul. 2015. (🄫2015 IEICE), Jun Shiomi, Tohru Ishihara, and Hidetoshi Onodera, “An Energy-Efficient On-Chip Memory Structure for Variability-Aware Near-Threshold Operation, ” in International Symposium on Quality Electronic Design, Mar. 2015, pp. 23–28. (🄫2015 IEEE), Jun Shiomi, Tohru Ishihara, and Hidetoshi Onodera, “Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design, ” in Asia and South Pacific Design Automation Conference, Jan. 2015, pp. 87–93. (🄫2015 IEEE), Figure 2.2: The definition of kσ worst case delay.(🄫2015 IEICE), Figure 3.1: Definition of averaging effect ratio.(🄫2015 IEICE), Figure 3.2: Buffer chain example where all buffers have the same fan-out. (🄫2015 IEICE), Figure 3.3: Buffer chain simulation result (VDD = 0.4 V). μ = - 21, σ = 0.21 and r = 0.32. (🄫2015 IEICE), Figure 3.4: Averaging effect ratio for buffer chains. (🄫2015 IEICE), Figure 3.5: Logic depth vs. the 4σ worst case delay. (🄫2015 IEICE), Figure 3.6: Parallelism of 8-stage-buffer chains. (🄫2015 IEICE), Figure 3.7: The number of critical paths Ncp vs. the 3σ worst case delay. The logic depth is 8. (🄫2015 IEICE), Figure 3.8: The number of critical paths Ncp vs. the 3σ worst case delay. The logic depth is 1. (🄫2015 IEEE), Figure 3.9: Delay distributions for different gate sizes. (🄫2015 IEICE), Figure 3.10: Buffer size X vs. 4σ worst case delay. (🄫2015 IEICE), Figure 3.11: The 4σ worst case delay for different gate sizes. (🄫2015 IEICE), Figure 3.12: Test circuit structure for NAND2 and NOR2. (🄫2015 IEICE), Figure 3.13: Averaging effect ratio for NAND2/NOR2 chains. (🄫2015 IEICE), Figure 3.14: Logic depth vs. 4σ worst case delay for NAND2/NOR2 chains. (🄫2015 IEICE), Figure 3.15: The number of critical paths Ncp vs. the 3σ worst case delay for NAND2/NOR2 chains. (🄫2015 IEICE), Figure 3.16: Gate size X vs. 4σ worst case delay for NAND2/NOR2 chains. (🄫2015 IEICE), Figure 3.17: The 4σ worst case delay of NAND2/NOR2 chains with different gate sizes. (🄫2015 IEICE), Figure 3.18: p-parallel n-stage buffer chains where all buffers in chains have the same gate size X. (🄫2015 IEICE), Figure 3.20: Memory readout structure. (a) SRAM (b) SCM. (🄫2015 IEEE), Figure 3.21: CDF versus readout delay. (🄫2015 IEEE), Figure 4.1: The concept of minimum height standard-cells. (🄫2017 Elsevier), Figure 4.2: An inverter cell with minimum cell height. (🄫2017 Elsevier), Figure 4.3: Simplified latch schematic and clock-shared 4-bit latch. (🄫2017 Elsevier), Figure 4.4: Proposed SCM structure. (🄫2017 Elsevier), Figure 4.5: Write clocking scheme of the proposed SCM. (🄫2017 Elsevier), Figure 4.6: Readout scheme of the proposed SCM. (🄫2017 Elsevier), Figure 4.7: (a) Schematic of cross-coupled inverters. (b) Butterfly curve of cross-coupled inverters. (🄫2017 Elsevier), Figure 4.8: Verification of the analytical stability model of latch cells (4.2). (🄫2017 Elsevier), Figure 4.9: Yields of latch cells for various gate widths. (🄫2017 Elsevier), Figure 4.10: The layout of minimum height standard-cells. (🄫2017 Elsevier), Figure 4.11: Layouts of the proposed 16 kb SCM (512 32). (🄫2017 Elsevier), Figure 4.12: Area-comparison between the proposed SCMs, prior-art SCMs and SRAMs. The area of the SCMs in [1] is multiplied by (100 nm=50 nm)2 = 4. (🄫2017 Elsevier), Figure 4.13: Estimated maximum operating frequency with a scaled VDD. (🄫2017 Elsevier), Figure 4.14: Estimated write energy consumption per bit with a scaled VDD. (🄫2017 Elsevier), Figure 4.15: Estimated read energy consumption per bit with a scaled VDD. (🄫2017 Elsevier), Figure 4.16: Estimated sleep energy consumption per bit with a scaled VDD. (🄫2017 Elsevier), Figure 4.17: Leakage power per bit with a scaled VDD. (🄫2017 Elsevier), Figure 5.2: Energy and performance contours for a 50-stage inverter chain. Solid line: energy contour. Dashed line: performance contour. Bold line: minimum energy curve. (🄫2017 IEICE), Figure 5.3: Minimum energy points in sub-threshold region. (🄫2017 IEICE), Figure 5.4: Minimum energy curve of a circuit designed with a 28-nm process technology. (🄫2017 IEICE), Figure 5.5: Minimum energy points in super-threshold region. (🄫2017 IEICE), Figure 5.6: Minimum energy curves for different temperature and activity. (🄫2017 IEICE), Figure 5.8: The SCM structure. (🄫2017 IEICE), Figure 5.9: Minimum energy curve of the SCM. Solid line: energy contour [nJ/cycle]. Dashed line: Fmax contour. Bold line: minimum energy curve. (🄫2017 IEICE), Figure 5.12: Ed/Es ratio on MEPs. (🄫2017 IEICE), Figure 5.13: Ed/Es ratio on 391 kHz Fmax contour. (🄫2017 IEICE), Figure 5.14: Ed/Es ratio on 8 MHz Fmax contour. (🄫2017 IEICE), Figure 5.15: Ed/Es ratio on 28.57 Hz Fmax contour. (🄫2017 IEICE), Figure 5.16: Definition of the parameter αM. (🄫2017 IEICE), Figure 5.17: Minimum energy curve of the SCM for αM = 0.1. Solid line: energy contour [nJ/cycle].Dashed line: Fmax contour. Bold line: minimum energy curves. (🄫2017 IEICE), Table 3.1: Summary of properties. C: Corollary. L: Lemma. T: Theorem. p: degree of parallelism. N: logic depth. W: gate width. L: gate length. STV: Super-Threshold Voltage. (🄫2015 IEICE), Table 4.1: 5.5-track minimum height standard cell library in the target 65-nm FD-SOI process technology. (🄫2017 Elsevier), Table 4.2: Comparison between Prior-Art SCMs and SRAMs. (🄫2017 Elsevier)

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