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Metody analýzy stavových automatů pro vestavné aplikace / Analysis of State Automatas for Embedded Applications

This master’s thesis deals with analysis of state machines for embedded applications. The issue of finite-state machine is described theoretically. The document also contains a proposal for funding for modeling finite state machines in Matlab/Simulink. It is designed data representation of finite automaton. Over this data representation algorithm of minimization is applied. Finally, the algorithm is implemented to generate code in C language.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:218940
Date January 2011
CreatorsMaťas, Marek
ContributorsBlaha, Petr, Václavek, Pavel
PublisherVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Source SetsCzech ETDs
LanguageSlovak
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

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