As semiconductor technology is scaled and voltage level is reduced, the impact
of the variation in power supply has become very significant in predicting the realistic
worst-case delays in integrated circuits. The analysis of power supply noise is inevitable
because high correlations exist between supply voltage and delay. Supply noise analysis
has often used a vector-based timing analysis approach. Finding a set of test vectors in
vector-based approaches, however, is very expensive, particularly during the design
phase, and becomes intractable for larger circuits in DSM technology.
In this work, two novel vectorless approaches are described such that increases
in circuit delay, because of power supply noise, can be efficiently, quickly estimated.
Experimental results on ISCAS89 circuits reveal the accuracy and efficiency of my
approaches: in s38417 benchmark circuits, errors on circuit delay distributions are less
than 2%, and both of my approaches are 67 times faster than the traditional vector-based
approach. Also, the results show the importance of considering care-bits, which sensitize
the longest paths during the power supply noise analysis.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-1902 |
| Date | 02 June 2009 |
| Creators | Kim, Hyun Sung |
| Contributors | Walker, Duncan M. H. |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Thesis, text |
| Format | electronic, application/pdf, born digital |
Page generated in 0.0039 seconds