Compressed bitmap indices are heavily used in scientific and commercial database systems because they largely improve query performance for various workloads. Early research focused on finding tailor-made index compression schemes that are amenable for modern processors. Improving performance further typically comes at the expense of a lower compression rate, which is in many applications not acceptable because of memory limitations. Alternatively, tailor-made hardware allows to achieve a performance that can only hardly be reached with software running on general-purpose CPUs. In this paper, we will show how to create a custom instruction set framework for compressed bitmap processing that is generic enough to implement most of the major compressed bitmap indices. For evaluation, we implemented WAH, PLWAH, and COMPAX operations using our framework and compared the resulting implementation to multiple state-of-the-art processors. We show that the custom-made bitmap processor achieves speedups of up to one order of magnitude by also using two orders of magnitude less energy compared to a modern energy-efficient Intel processor. Finally, we discuss how to embed our processor with database-specific instruction sets into database system environments.
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:82144 |
| Date | 18 January 2023 |
| Creators | Lehner, Wolfgang, Haas, Sebastian, Karnagel, Tomas, Arnold, Oliver, Laux, Erik, Schlegel, Benjamin, Fettweis, Gerhard |
| Publisher | IEEE |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | info:eu-repo/semantics/acceptedVersion, doc-type:conferenceObject, info:eu-repo/semantics/conferenceObject, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | 978-1-5090-1503-0, 10.1109/ASAP.2016.7760772, info:eu-repo/grantAgreement/Deutsche Forschungsgemeinschaft/Excellence 1056/692519 //Ultra-Low Power Technologies and Memory Architectures for IoT/PRIME |
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