In the microprocessor system, the bandwidth problems of instruction stream and data stream are the main causes that limit the performance of the system. Although cache can effectively smooth this problem, the processor still needs more than one clock cycle to get the data. The large hardware cost and power consumption also limit the cache in the embedded system applications. The buffering techniques, such as the loop buffer and the prefetch buffer, can improve the performance in low hardware. Their mechanisms emphasize on the buffering of the continuous data space. For the non-continuous data space accesses caused by the branch instructions, they cannot exploit the reference localities. In this thesis, we propose a new buffering mechanism called as the ABP buffer, which is composed of a buffering mechanism and a prefetching mechanism. The buffering mechanism can effectively buffer the non-continuous data space and replace the buffer lines in a replacement policy, which is suitable for hardware realization. The prefetching mechanism exploits the hit time to prefetch the data that can be used in near future. The simulation and implement results show that the ABP buffer can gain high performance in low hardware and the control parts of the mechanism only occupy 4% of the total hardware.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0625103-105712 |
| Date | 25 June 2003 |
| Creators | Wu, Chih-Kang |
| Contributors | Jih-ching Chiu, Shie-Jue Lee, Shen-Fu Hsiao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625103-105712 |
| Rights | unrestricted, Copyright information available at source archive |
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