In order to assess and optimize layout strategies for minimizing substrate noise, it is necessary to have fast and accurate techniques for computing contact coupling resistances associated with the substrate. In this talk, we describe an extraction method capable of full-chip analysis which combines modest geometric approximations, a novel integral formulation, and an FFT-accelerated preconditioned iterative method. / Singapore-MIT Alliance (SMA)
| Identifer | oai:union.ndltd.org:MIT/oai:dspace.mit.edu:1721.1/3923 |
| Date | 01 1900 |
| Creators | Vithayathil, Anne, Hu, Xin, White, Jacob K. |
| Source Sets | M.I.T. Theses and Dissertation |
| Language | en_US |
| Detected Language | English |
| Type | Article |
| Format | 10535 bytes, application/pdf |
| Relation | High Performance Computation for Engineered Systems (HPCES); |
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