Thesis (PhD)--University of Stellenbosch, 2004. / ENGLISH ABSTRACT: Analog-to-digital converters (ADCs) are an integral part of the interface between the analog and
digital realms. This dissertation presents the design and simulation of a Complementary Output
Switching-Logic (COSL) compatible, voltage state, switching logic comparator and a flash ADC
for high speed applications with multi-GHz input bandwidth. Josephson technology and the
COSL family of gates were utilized for this purpose.
A detailed design for the switching logic comparator is first provided. The design is verified with
simulations to obtain a functional comparator. The comparator is then optimized utilizing an
optimization tool developed using the scripting facilities of WRSpice. Incorporated in this tool
is a Monte Carlo capability to randomly vary the component values according to Gaussian
distributions, and trimming facilities to be able to trim a non-functional comparator to restore
functionality. The design component values are then optimized by maximizing the yield of a
comparator.
The optimized comparator is incorporated into the construction of a4-bit quantizer of an ADC.
The output from the quantizer section yields a switching-logic Gray-code output. A Gray-to-
Binary converter is designed with COSL gates to convert the Gray output from the quantizer into
Binary code for further processing.
The functionality, linearity, maximum input bandwidth and dynamic range of the 4-bit ADC is
verified by simulation. A number of special input waveforms are used for this purpose. The
performance of the comparator and the 4-bit ADC is also evaluated with thermal noise
incorporated into simulation. Beat frequency simulations and Fourier spectra were also used
in the evaluation of the ADC performance.
A fully functional 4-bit ADC, with a maximum input bandwidth of 10 GHz for a clock speed of
20 GHz was achieved through simulations. Beat frequency simulations revealed that the
comparators have an input bandwidth greater than 19 GHz with sufficient dynamic range for an
ADC of greater than 6 bits of resolution.
Due to the fact that the aperture time for the ADC is dependant on the rise time of the sampling
pulse and not the width of the pulse, a much smaller aperture time is obtained which directly
translates to higher input bandwidth.
Finally, a layout of a 4-bit sampler circuit was done according to the Hypres manufacturing
process to enable the high-speed testing of the comparator circuits. / AFRIKAANSE OPSOMMING: Analoog-na-Digitale Omsetters (ADOs) vorm 'n integrale deel van die koppelvlak tussen die
analoog en digitale wêrelde. Hiedie proefskrif stel die ontwerp en simulasie van 'n
Komplementêre Uittree Geskakelde Logika (COSL) aanpasbare, spanningstoestand,
geskakelde logika vergelyker en ADO bekend. Hierdie ADO kan vir hoë spoed toepassings
waar multi-GHz intree-bandwydte benodig word, aangewend word. Josephson tegnologie en
die Komplementêre Uittree Geskakelde Logika (COSL) familie van hekke word vir hierdie doel
gebruik.
Die volledige ontwerp vir die geskakelde logika vergelyker word eerstens gegee. Die ontwerp
word met behulp van simulasies bevestig om sodoende 'n ten volle funksionele vergelyker te
verkry. Die vergelyker word verder geëptimeer deur middel van 'n proses wat met behulp van
programmering in WRSpice ontwikkel is. Hierdie optimeringsproses sluit 'n Monte Carlo proses
in wat die komponentwaardes van die vergelyker onwillekeurig volgens 'n Gaussiese
verspreiding verander, sowel as 'n verstellingsmeganisme waarmee 'n nie-funksionerende
vergelyker verstel kan word totdat dit weer ten volle funksioneer. Die komponentwaardes word
dan geëptimeer vir maksimale opbrengs van 'n vergelyker.
Die geëptimeerde vergelyker word gebruik in die konstruksie van 'n 4-bis kwantifiseerder vir 'n
ADO. Die uittree van die 4-bis kwantifiseerder is in Gray kode. 'n Gray-na-Binêre kode omsetter
word vir hierdie doelontwerp deur van COSL hekke gebruik te maak.
Die volle ADO word voorts gesimuleer om die funksionalitet, lineariteit, maksimum
intreebandwydte en dinamiese bereik te verifieer. 'n Verskeidenheid van intreeseine is vir
hierdie doel gebruik. Die vergelyker en die 4-bis ADO is ook gesimuleer met termiese ruis om
die effek daarvan te bepaal. Fourier spektra en ''verskilfrekwensie'' (Beat Frequency) simulasies
word ook gebruik in die evaluering van die vergelyker en die ADO.
Die korrekte werking van 'n 4-bis ADO met intreebandwydte van 10 GHz met 'n klokspoed van
20 GHz is deur simulasie bevestig. Verskilfrekwensie simulasies dui aan dat die vergelykers 'n
intreebandwydte van groter as 19 GHz het, met voldoende dinamiese bereik vir 6 bis resolusie.
Aangesien die vergelykers se venstertydperk bepaal word deur die stygende helling van die
monsterpuls en nie deur die pulswydte nie, maak dit voorsiening vir 'n baie klein venstertydperk.
'n Klein venstertydperk is essensieel vir 'n hoë intreebandwydte.
'n Uitleg van 'n 4-bis vergelyker stadium is gedoen vir die Hypres vervaardigingsproses om die
vergelyker teen hoë spoed te kan toets.
| Identifer | oai:union.ndltd.org:netd.ac.za/oai:union.ndltd.org:sun/oai:scholar.sun.ac.za:10019.1/53765 |
| Date | 04 1900 |
| Creators | Powell, I. A. (Ian Allan) |
| Contributors | Perold, W. J., Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering. |
| Publisher | Stellenbosch : Stellenbosch University |
| Source Sets | South African National ETD Portal |
| Language | en_ZA |
| Detected Language | English |
| Type | Thesis |
| Format | 120 p. : ill. |
| Rights | Stellenbosch University |
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