The work deals with the design of novel high order sigma-delta AD converter using switched-capacitors approach. Model of the ideal and real architecture of the third order sigma-delta modulator was designed in MATLAB SIMULINK. The comparison of the ideal and real model of sigma delta architecture is described in this thesis. On the basis of simulation results in MATLAB SIMULINK the stages of modulator on transistors level in CMOS technology were designed. Fully differential operational amplifier, switched capacitor integrator, summing amplifier, comparator, one bit digital to analog converter and nonoverlapping clock generator were designed. The circuit of third order sigma-delta modulator was simulated in CADENCE. Layout of operational amplifier and switched capacitor integrator was made. Through the use of MATLAB was designed decimation filter as well.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:217731 |
| Date | January 2008 |
| Creators | Forejtek, Jiří |
| Contributors | Fujcik, Lukáš, Háze, Jiří |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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