The thesis focuses on a higher order noise-shaping Δ ADC architecture which employs filtered quantization error as a dither signal. Furthermore, the work studies implementation challenges using Switched-Capacitor and Switched-Current techniques.
Digitization in an IF conversion receiver can be accomplished either with a wide band Nyquist rate ADC or a BandPass Δ ADC. The use of the latter is the optimum solution since the bandwidth of the IF signals is typically much smaller than the carrier frequency and reducing the quantization noise in the entire nyquist band becomes superfluous. Instead by using BandPass Δ ADCs the quantization noise power is reduced only in a narrow band around IF location. We study state-of-the-art high dynamic range Δ data converter topologies suited for wide-band radio receivers. We propose a topology which achieves higher order noise shaping by employing filtered quantization error as a dither signal.
We study implementation challenges for Δ converters in digital technology. Traditionally, Δ ADCs used Switched-Capacitor (SC) circuits to realize their building blocks. This analog sample-data technique is based on the idea that a periodically switched capacitor can emulate a resistor. The limiting factor that degrades the performance of SC circuits implemented in standard VLSI technologies is the continuous reduction of supply voltages, prompted by the continuous scaling-down process. This fact, which is advantageous for digital circuitry, makes the design of SC circuits difficult, which are forced to use clock boosting strategies for switches and to increase the power consumption in order to obtain high-speed and high dynamic range opamps with low voltage operation. In this scenario, the use of current-domain sampled data technique, also named Switched-Current (SI), instead of voltages results advantageous for several reasons. As the signal carriers are currents, the supply voltage does not limit the signal range as much as in SC circuits. Therefore, SI circuits are more suitable than SC for low-voltage operation. This work studies the feasibility and bottlenecks of implementing Δ modulator building blocks using SI technique. A BandPass filter, DAC and 1-bit quantizer have been designed in 0.18µm technology using SI technique. (For mathematical equations pl refer the pdf file)
| Identifer | oai:union.ndltd.org:IISc/oai:etd.ncsi.iisc.ernet.in:2005/712 |
| Date | 01 March 2008 |
| Creators | Behera, Khitish Chandra |
| Contributors | Jamadagni, H S |
| Source Sets | India Institute of Science |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Relation | G22174 |
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