This thesis describes design techniques for high-performance switched-capacitor
(SC) circuits, primarily for high-linearity low-noise SC circuits in the presence of
component imperfections, such as nonlinear op-amp voltage transfer characteristics,
capacitor nonlinearities as well as the finite op-amp dc gain and op-amp offset and noise.
Various correlated-double-sampling (CDS) schemes are discussed, and some novel
predictive CDS schemes are proposed. Analysis, simulation and experimental results show
that these schemes are very effective for reducing the effects of op-amp imperfections,
resulting in lower signal distortion and reduced low-frequency noise and dc offset. The
effect of capacitor nonlinearity in an SC circuits is analyzed in detail, and techniques for
linearization are discussed. Applying these techniques, MOSFET capacitors can be used in
high-performance digital-process-compatible SC circuit designs.
To verify the effectiveness of the proposed techniques, three prototype chips
containing a 3-V all-MOSFET delta-sigma modulator, predictive gain- and offset-compensated
track-and-hold stages, and SC amplifiers with various CDS techniques, were
designed and fabricated in 1.2 ��m CMOS technology. The measured results show that
these circuit techniques are highly effective in high-performance SC circuit designs. / Graduation date: 1997
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/34477 |
| Date | 06 March 1997 |
| Creators | Huang, Yunteng |
| Contributors | Temes, Gabor C. |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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