Switched-capacitor (SC) circuits are commonly used for analog signal processing
because they can be used to realize precision filters and data converters on an
integrated circuit (IC). However, for high speed applications SC circuit operating
speeds are limited by the internally-compensated opamps found in SC integrators,
a common building block of these circuits. This thesis studies gain stages that
eliminate the internal compensation, thus allowing the SC circuits to operate at
significantly higher operating speeds. An inverter-based SC integrator is presented.
The proposed SC integrator is built with a pseudo-differential structure to improve
its rejection of common-mode noise, such as charge injection and clock feedthrough.
The proposed integrator also incorporates correlated double sampling (CDS) to
boost its effective DC gain. Clock-boosting and switch bootstrapping techniques
are not used in the proposed circuit, even though it uses a low supply voltage.
To verify the speed advantage of the proposed circuit, a high speed delta sigma
(Δ∑) modulator was designed in a 1.8V, 0.18μm CMOS technology. The designed
Δ∑ modulator operates at a clock frequency of 500MHz. Circuit implementation
and layout floorplan are described. The design is based on MATLAB and SpectreS
simulations. / Graduation date: 2002
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/29055 |
| Date | 23 August 2001 |
| Creators | Thomas, Daniel E. |
| Contributors | Moon, Un-Ku, Temes, Gabor C. |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
Page generated in 0.0014 seconds