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Multiple clock domain synchronization for network on chips

Thesis (M.S. in computer engineering)--Washington State University, December 2007. / Includes bibliographical references (p. 54-58).

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/183728971
Date January 2007
CreatorsSarkar, Souradip,
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceOnline access for everyone

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