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Automated mapping of clocked logic to quasi-delay insensitive circuits

Thesis (Ph.D.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/434742090
Date January 2007
CreatorsShivakumaraiah, Lokesh,
PublisherMississippi State : Mississippi State University,
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
TypeElectronic resources. Electronic theses/dissertations. Master's theses.

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