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High level techniques for leakage power estimation and optimization in VLSI ASICs [electronic resource] / by Chandramouli Gopalakrishnan.

Title from PDF of title page. / Document formatted into pages; contains 124 pages. / Thesis (Ph.D.)--University of South Florida, 2003. / Includes bibliographical references. / Text (Electronic thesis) in PDF format. / ABSTRACT: As technology scales down and CMOS circuits are powered by lower supply voltages, standby leakage current becomes significant. A behavioral level framework for the synthesis of data-paths with low leakage power is presented. There has been minimal work done on the behavioral synthesis of low leakage datapaths. We present a fast architectural simulator for leakage (FASL) to estimate the leakage power dissipated by a system described hierarchically in VHDL. FASL uses a leakage power model embedded into VHDL leafcells. These leafcells are characterized for leakage accurately using HSPICE. We present results which show that FASL measures leakage power significantly faster than HSPICE, with less than a 5% loss in accuracy, compared to HSPICE. We present a comprehensive framework for synthesizing low leakage power data-paths using a parameterized Multi-threshold CMOS (MTCMOS) component library. / ABSTRACT: The component library has been characterized for leakage power and delay as a function of sleep transistor width. We propose four techniques for minimization of leakage power during behavioral synthesis: (1) leakage power management using MTCMOS modules; (2) an allocation and binding algorithm for low leakage based on clique partitioning; (3) selective binding to MTCMOS technology, allowing the designer to have control over the area overhead; and (4) a performance recovery technique based on multi-cycling and introduction of slack, to alleviate the loss in performance attributed to the introduction of MTCMOS modules in the data-path. Finally, we propose two iterative search based techniques, based on Tabu search, to synthesize low leakage data-paths. The first technique searches for low leakage scheduling options. The second technique simultaneously searches for a low leakage schedule and binding. It is shown that the latter technique of unified search is more robust. / ABSTRACT: The quality of results generated bytabu-based technique are superior to those generated by simulated annealing (SA) search technique. / System requirements: World Wide Web browser and PDF reader. / Mode of access: World Wide Web.

Identiferoai:union.ndltd.org:USF/oai:palmm.fcla.edu:AJM5914SEB
Date January 2003
CreatorsGopalakrishnan, Chandramouli.
PublisherUniversity of South Florida
Source SetsUniversity of South Flordia
Detected LanguageEnglish

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