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Full utilization, fairness, and access delay on high speed slotted bus networks

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997. / Includes bibliographical references (p. 89-92). / Supported by the U.S. Army Research Office. ARO ASSERT DAAH04-94-G-0221 Supported by National Science Foundation. NCR-92036379 Supported by Advanced Research Project Agency. MDA972-92-J-1038 / Chiu, A.L. / Ph.D.

Identiferoai:union.ndltd.org:MIT/oai:dspace.mit.edu:1721.1/10699
Date January 1997
CreatorsChiu, Angela Lan
ContributorsMassachusetts Institute of Technology. Laboratory for Information and Decision Systems., Massachusetts Institute of Technology. Laboratory for Information and Decision Systems, Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
PublisherMassachusetts Institute of Technology, Laboratory for Information and Decision Systems, Massachusetts Institute of Technology
Source SetsM.I.T. Theses and Dissertation
LanguageEnglish
Detected LanguageEnglish
TypeThesis
Format92 p., 4619469 bytes, 4619227 bytes, application/pdf, application/pdf, application/pdf
RightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission., http://dspace.mit.edu/handle/1721.1/7582
RelationLIDS-P ; 2382.

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