Basic methodology that exploits instruction level parallelism is called pipelining and it is part of every processor for decades. The ideal pipeline increases performance and efficiency for a relatively small cost. But the real pipeline has number of limitations caused by dependencies and hazards between instructions. The aim of this thesis is to discuss techniques used to improve efficency and performance of pipelined processors, to implement selected techniques to a RISC processor model and discuss its benefits.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:413231 |
| Date | January 2020 |
| Creators | Sláma, Pavel |
| Contributors | Levek, Vladimír, Pristach, Marián |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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