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Efficient approaches in interconnect-driven floorplanning.

Lai Tsz Wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 123-129). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Cycle --- p.2 / Chapter 1.2 --- Physical Design Cycle --- p.4 / Chapter 1.3 --- Floorplanning --- p.7 / Chapter 1.3.1 --- Types of Floorplan and Floorplan Representations --- p.11 / Chapter 1.3.2 --- Interconnect-driven Floorplanning --- p.13 / Chapter 1.4 --- Motivations and Contributions --- p.17 / Chapter 1.5 --- Organization of this Thesis --- p.18 / Chapter 2 --- Literature Review on Floorplan Representation --- p.20 / Chapter 2.1 --- Slicing Floorplan Representation --- p.20 / Chapter 2.1.1 --- Normalized Polish Expression --- p.20 / Chapter 2.2 --- Non-slicing Floorplan Representations --- p.21 / Chapter 2.2.1 --- Sequence Pair (SP) --- p.21 / Chapter 2.2.2 --- Bounded-sliceline Grid (BSG) --- p.23 / Chapter 2.2.3 --- O-tree --- p.25 / Chapter 2.2.4 --- B*-tree --- p.26 / Chapter 2.3 --- Mosaic Floorplan Representations --- p.28 / Chapter 2.3.1 --- Corner Block List (CBL) --- p.28 / Chapter 2.3.2 --- Twin Binary Trees (TBT) --- p.31 / Chapter 2.3.3 --- Twin Binary Sequences (TBS) --- p.32 / Chapter 2.4 --- Summary --- p.34 / Chapter 3 --- Literature Review on Interconnect Optimization in Floorplan- ning --- p.37 / Chapter 3.1 --- Wirelength Estimation --- p.37 / Chapter 3.2 --- Congestion Optimization --- p.38 / Chapter 3.2.1 --- Integrated Floorplanning and Interconnect Planning --- p.41 / Chapter 3.2.2 --- Multi-layer Global Wiring Planning (GWP) --- p.43 / Chapter 3.2.3 --- Estimating Routing Congestion using Probabilistic Anal- ysis --- p.44 / Chapter 3.2.4 --- Congestion Minimization During Placement --- p.46 / Chapter 3.2.5 --- Modelling and Minimization of Routing Congestion --- p.48 / Chapter 3.3 --- Buffer Planning --- p.49 / Chapter 3.3.1 --- Buffer Clustering with Feasible Region --- p.51 / Chapter 3.3.2 --- Routability-driven Repeater Clustering Algorithm with Iterative Deletion --- p.55 / Chapter 3.3.3 --- Planning Buffer Locations by Network Flow --- p.58 / Chapter 3.3.4 --- Buffer Planning using Integer Multicommodity Flow --- p.60 / Chapter 3.3.5 --- Buffer Planning Problem using Tile Graph --- p.60 / Chapter 3.3.6 --- Probabilistic Analysis for Buffer Block Planning --- p.62 / Chapter 3.3.7 --- Fast Buffer Planning and Congestion Optimization --- p.63 / Chapter 3.4 --- Summary --- p.66 / Chapter 4 --- Congestion Evaluation: Wire Density Model --- p.68 / Chapter 4.1 --- Introduction --- p.68 / Chapter 4.2 --- Overview of Our Floorplanner --- p.70 / Chapter 4.3 --- Wire Density Model --- p.71 / Chapter 4.3.1 --- Computation of Ni --- p.72 / Chapter 4.3.2 --- Computation of Pi --- p.74 / Chapter 4.3.3 --- Usage of Mirror TBT --- p.76 / Chapter 4.4 --- Implementation --- p.76 / Chapter 4.4.1 --- Efficient Calculation of Ni --- p.76 / Chapter 4.4.2 --- Solving the LCA Problem Efficiently --- p.81 / Chapter 4.4.3 --- Cost Function --- p.81 / Chapter 4.4.4 --- Complexity --- p.81 / Chapter 4.5 --- Experimental Results --- p.82 / Chapter 4.6 --- Conclusion --- p.83 / Chapter 5 --- Buffer Planning: Simple Buffer Planning Method --- p.85 / Chapter 5.1 --- Introduction --- p.85 / Chapter 5.2 --- Variable Interval Buffer Insertion Constraint --- p.87 / Chapter 5.3 --- Overview of Our Floorplanner --- p.88 / Chapter 5.4 --- Buffer Planning --- p.89 / Chapter 5.4.1 --- Feasible Grids --- p.89 / Chapter 5.4.2 --- Table Look-up Approach --- p.89 / Chapter 5.5 --- Implementation --- p.91 / Chapter 5.5.1 --- Building the Look-up Tables --- p.91 / Chapter 5.5.2 --- An Example of Look-up Table Construction --- p.94 / Chapter 5.5.3 --- A Faster Approach for Building the Look-up Tables --- p.101 / Chapter 5.5.4 --- An Example of the Faster Look-up Table Construction --- p.105 / Chapter 5.5.5 --- I/O Pin Locations --- p.106 / Chapter 5.5.6 --- Cost Function --- p.110 / Chapter 5.5.7 --- Complexity --- p.111 / Chapter 5.6 --- Experimental Results --- p.112 / Chapter 5.6.1 --- Selected Value for A --- p.112 / Chapter 5.6.2 --- Performance of Our Floorplanner --- p.113 / Chapter 5.7 --- Conclusion --- p.116 / Chapter 6 --- Conclusion --- p.118 / Chapter A --- An Efficient Algorithm for the Least Common Ancestor Prob- lem --- p.120 / Bibliography --- p.123

Identiferoai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_324222
Date January 2003
ContributorsLai, Tsz Wai., Chinese University of Hong Kong Graduate School. Division of Computer Science and Engineering.
Source SetsThe Chinese University of Hong Kong
LanguageEnglish, Chinese
Detected LanguageEnglish
TypeText, bibliography
Formatprint, xi, 129 leaves : ill. ; 30 cm.
RightsUse of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/)

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