A novel design methodology of parallel VLSI matrix transposer circuit based on a multi-bank memory architecture is presented. The proposed transposer design is especially suitable for large matrix applications where the use of registers to store the matrix data become inefficient. Due to the limited access ports of single SRAM module, this paper first proposes a two-way group expansion bank allocation algorithm such that each of the input or the output data presented in each cycle belongs to separate banks of memory. Next, the allocation results can be further utilized to automatically synthesize the input and output data-path router based on a two-level data switch architecture. Finally, a dedicated data fetch address generator circuit is also proposed, which divides the address generation into two parts. These parts include group base and offset address generation which can be simply realized by a shift-register array and a small on-chip ROM table, respectively. The proposed design methodology has been implemented as a systematic transposer generator which can generate the soft Verilog code. It can generate very fast transposer which can run at one hundred fifty mega hertz. Our experimental results from several design cases show that our multi-bank memory based transposer can consume much less gates compared with register-based transposer architecture.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0904109-113406 |
| Date | 04 September 2009 |
| Creators | Lin, Chueh-Ting |
| Contributors | Chuen-Yau Chen, Yun-Nan Chang, Shiann-Rong Kuang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406 |
| Rights | campus_withheld, Copyright information available at source archive |
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