The thesis proposes using the efficient memory arrangement methods for the implementation of radix-r multi-dimensional Discrete Fourier Transform (DFT) and Discrete Cosine Transform (DCT). By using the memory instead of the registers to buffer and reorder data, hardware complexity is significantly reduced. We use the recursive architecture that requires only one arithmetic-processing element to compute the entire DFT/DCT operation. The algorithm is based on efficient coefficient matrix factorization and data allocation. By exploiting the features of Kronecker product representation in the fast algorithm, the multi-dimensional DFT/DCT operation is converted into its corresponding 1-D problem and the intermediate data is stored in several memory units. In addition to the smaller area, we also propose a method to reduce the power consumption of the DFT/DCT processors.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0724101-181423 |
| Date | 24 July 2001 |
| Creators | Hsu, Fang-Chii |
| Contributors | Yeong-Kang Lai, Ing-Jer Huang, Shen-Fu Hsiao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724101-181423 |
| Rights | campus_withheld, Copyright information available at source archive |
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