Thesis (MScEng (Electrical and Electronic Engineering))--Stellenbosch University, 2011. / ENGLISH ABSTRACT: This thesis investigates the viability of constructing a solid-state transformer (SST) with
a series-input, parallel-output connection of full-bridge, three-level
ying-capacitor converters.
It focusses on the active recti er front-end of the SST which is used to control
the input current to be sinusoidal and in-phase with the sinusoidal input voltage. A stack
of two converters are built and tested. The input current, as well as the
ying capacitor
voltages of the two active recti ers in the stack, are actively controlled by a nite-state
model-based predictive (FS-MPC) controller.
The use of multiple
ying-capacitor converters poses a problem when using FS-MPC
because of the large number of possible switching states to include in the prediction
equations. Three FS-MPC control algorithms are proposed to attempt to overcome the
problem associated with the large number of switching states. They are implemented
on an FPGA digital controller. The algorithms are compared on the bases of voltage
and current errors, as well as their responses to disturbances that are introduced into
the system. The simulation and experimental results that are presented shows that by
interleaving the control actions for the two converters, one can obtain fast and robust
responses of the controlled variables. The viability of extending the interleaving control
algorithm beyond two converters is also motivated. / AFRIKAANSE OPSOMMING: Hierdie tesis ondersoek die moontlikheid van volbrug, drievlak vlieënde-kapasitoromsetters
wat gebruik word om 'n serie-intree, parallel-uittree drywingselektroniese transformator
(DET) te bou. Dit fokus op die aktiewe gelykrigter van die DET wat gebruik word om
die intreestroom te beheer om sinusvormig en in fase met die sinusvormige intreespanning
te wees. 'n Stapel van twee omsetters word gebou en getoets. Die intreestroom,
sowel as die vlieënde kapasitorspannings van die twee aktiewe gelykrigters in die stapel,
word aktief beheer met behulp van 'n eindige-toestand, model-gebaseerde voorspellende
beheerder (ET-MVB).
Die gebruik van veelvuldige vlieënde-kapasitoromsetters bemoeilik die implementering van
'n ET-MVB-beheerder as gevolg van die groot aantal skakeltoestande wat in die voorspellende
vergelykings in ag geneem moet word. Drie ET-MVB-algoritmes word voorgestel
om te poog om die probleme, wat met die groot aantal skakeltoestande geassosieer word,
te oorkom. Die algoritmes word in 'n FPGA digitale verwerker geïmplementeer. Die
algoritmes word vergelyk op grond van hul stroom- en spanningsfoute, asook hul reaksie
op steurings wat op die stelsel ingevoer word. Die simulasie en praktiese resultate toon
dat, deur die beheeraksies vir die twee omsetters te laat oorvleuel, die gedrag van die beheerde
veranderlikes vinniger en meer robuust is. Die moontlikheid om die oorvleuelende
beheeraksies uit te brei tot meer as twee omsetters word ook gemotiveer.
| Identifer | oai:union.ndltd.org:netd.ac.za/oai:union.ndltd.org:sun/oai:scholar.sun.ac.za:10019.1/18087 |
| Date | 12 1900 |
| Creators | Du Toit, Daniel Josias |
| Contributors | Mouton, H. du T., Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering. |
| Publisher | Stellenbosch : Stellenbosch University |
| Source Sets | South African National ETD Portal |
| Language | en_ZA |
| Detected Language | English |
| Type | Thesis |
| Format | 154 p. : ill. |
| Rights | Stellenbosch University |
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