In this thesis, we will investigate the degradation of the Low-Temperature-Polycrystalline-Silicon TFTs(LTPS TFTS) under the electrical stress. The devices are offer by Chi Mei Optoelectronics. The two mechanisms of the electrical stress are ac and dc stress. On the dc stress, we can separate the two degradation mechanisms from fixed drain voltage and various the gate voltage. The first mechanism is hot carrier effect, and second is self-heating effect. We were study the degradation mechanisms cause by above-mentioned phenomenon. On the other hand, we were confirmed the position and type of the defects by measured capacitance.
In the ac stress, device degradation depends on the emission rate and energy of the hot carrier. We will study the degradation mechanism which fixed the drain voltage and various the Vg_low and falling time under different temperature. Another way of the ac stress condition will be used here. The drain and source are directly connected to ground. The gate is directly connected to the pulse. At this stress condition, carrier will push to the junction near the drain and source when gate pulse is switch from high to low. This degradation mechanism is the function of the temperature. We are going to employ a C-V measurement to examination of the defect cause by stress.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0728107-020059 |
| Date | 28 July 2007 |
| Creators | Lin, Chia-Sheng |
| Contributors | Ting-Chang Chang, Yeu-Long Jiang, Wei-Chou Hsu, YUH-FUNG HUANG, Uerng-Yih Ueng |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728107-020059 |
| Rights | not_available, Copyright information available at source archive |
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