Current task-centric many-core schedulers share a “naive” view of processor architecture; a view that does not care about its thermal, architectural or power consuming properties. Future processor will be more heterogeneous than what we see today, and following Moore’s law of transistor doubling, we foresee an increase in power consumption and thus temperature. Thermal stress can induce errors in processors, and so a common way to counter this is by slowing the processor down; something task-centric schedulers should strive to avoid. The Thermal-Task-Interleaving scheduling algorithm proposed in this paper takes both the application temperature behavior and architecture into account when making decisions. We show that for a mixed workload, our scheduler outperforms some of the standard, architecture-unaware scheduling solutions existing today. / QC 20120215
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:kth-89634 |
| Date | January 2011 |
| Creators | Podobas, Artur, Brorsson, Mats |
| Publisher | KTH, Programvaru- och datorsystem, SCS, KTH, Programvaru- och datorsystem, SCS |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Conference paper, info:eu-repo/semantics/conferenceObject, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | http://faspp.ac.upc.edu/faspp11/ |
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