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Transistor level synthesis and hierarchical timing optimization for CMOS combinational circuits /

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 118-126). Available also in a digital version from Dissertation Abstracts.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/46484543
Date January 1999
CreatorsLiu, Chia-pin Robin.
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceDigital version accessible at:

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