Electrical power demand in aircraft has grown significantly over the last century, and this trend continues with the More Electric Aircraft (MEA) and All Electric Aircraft (AEA) concepts. Higher voltages such as 270VDC are required to deliver additional power to loads and to optimise aircraft mass. Increased voltages inflict more stress on the Electrical Wiring Interconnect System (EWIS) and increase the impact of series arc faults caused by wiring defects. Solid State Power Controllers (SSPCs) are used to provide fast protection in high voltage distribution systems. The aim of this work is the characterisation, modelling, simulation and detection of series arc faults in 28VDC and 270VDC electrical power distribution systems featuring SSPCs. The majority of passive detection schemes in the literature were designed based on empirical data rather than well characterised electric arc parameters, and thus nuisance trips are unavoidable. To address this series arc faults in 28VDC and 270VDC solid state power distribution systems were characterised using the SAE5692 "Loose terminal" method [8], and it was found that 270VDC arc faults cause a minimal ~5.6% reduction in loop current and load voltage compared with ~54% in 28VDC systems. SSPC output voltage transients caused by series arcs were found to be limited by the presence of SSPC snubbers. Increasing the system loop inductance was found to improve series arc stability resulting in fewer arc quench events. Increasing the capacitive load reduces arc stability and causes arcs to quench more readily thus simplifying detection. These results were later used to experimentally validate a novel series arc fault SPICE model based on the static Nottingham V-I model [9] and wider solid state electrical system model. The arc current and SSPC output voltage results were also used to create a prototype passive series arc fault detection system, which has been demonstrated to SAE5692 under laboratory conditions [8]. A novel multilayer PCB current sensor was developed and experimentally validated for this prototype. To further reduce nuisance trips an innovative active arc fault perturbation scheme was simulated and experimentally demonstrated using SSPC modulation to stimulate and detect arc quench. Another novel complementary series arc fault prevention / confirmation scheme was simulated and experimentally validated using SSPC leakage currents. To minimise nuisance trips due to manufacturing and installation errors a unique Built-In Test (BIT) scheme was also developed and experimentally validated using the SSPC to create artificial current and voltage stimuli.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:690505 |
| Date | January 2016 |
| Creators | Handy, Peter James |
| Publisher | University of Warwick |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Source | http://wrap.warwick.ac.uk/80134/ |
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