Microprocessors have experienced a significant stall in single-thread performance since about 2004. Instead of significant annual performance improvements for a single core, it is easier to increase performance by providing multiple, independent cores that the application programmer has to coordinate. Exposing concurrency to the applications requires mechanisms to control it. Hardware Transactional Memory (HTM) is an abstraction that provides optimistic, fine-grained concurrency control with a simple application interface, and has received significant research attentions fro 2004 - 2010, with initial publications in the mid-90s.
The central thesis of my work is that detailed analysis and ISA modelling of HTM is necessary to understand actual implementation and usage challenges, and get more realistic results. Instead of overly complicating the design of HTM with features that would be extremely hard to implement right in a more detailed microarchitecture and ISA proposal, I suggest that getting a base-line HTM specification and micro-architecture right is a challenge in itself. Yet, despite the complexity, there are interesting implementation options and extensions that can provide benefits to applications using HTM–but they are not on the trajectory taken by most papers published between 2004 and 2010.
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:34473 |
| Date | 10 July 2019 |
| Creators | Diestelhorst, Stephan |
| Contributors | Fetzer, Christof, Romano, Paolo, Felber, Pascal, Technische Universität Dresden |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | info:eu-repo/semantics/publishedVersion, doc-type:doctoralThesis, info:eu-repo/semantics/doctoralThesis, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
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