by Johnson, Tin-Chak Pang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references. / Acknowledgments / Abstract / List of figures / List of tables / Chapter 1. --- Introduction --- p.1-1 / Chapter 1.1 --- Introduction --- p.1-1 / Chapter 1.2 --- Introduction to asynchronous system --- p.1-5 / Chapter 1.2.1 --- Motivation --- p.1-5 / Chapter 1.2.2 --- Hazards --- p.1-7 / Chapter 1.2.3 --- Classes of Asynchronous circuits --- p.1-8 / Chapter 1.3 --- Introduction to Transform Coding --- p.1-9 / Chapter 1.4 --- Organization of the Thesis --- p.1-16 / Chapter 2. --- Asynchronous Design Methodologies --- p.2-1 / Chapter 2.1 --- Introduction --- p.2-1 / Chapter 2.2 --- Self-timed system --- p.2-2 / Chapter 2.3 --- DCVSL Methodology --- p.2-4 / Chapter 2.3.1 --- DCVSL gate --- p.2-5 / Chapter 2.3.2 --- Handshake Control --- p.2-7 / Chapter 2.4 --- Micropipeline Methodology --- p.2-11 / Chapter 2.4.1 --- Summary of previous design --- p.2-12 / Chapter 2.4.2 --- New Micropipeline structure and improvements --- p.2-17 / Chapter 2.4.2.1 --- Asymmetrical delay --- p.2-20 / Chapter 2.4.2.2 --- Variable Delay and Delay Value Selection --- p.2-22 / Chapter 2.5 --- Comparison between DCVSL and Micropipeline --- p.2-25 / Chapter 3. --- Self-timed Multipliers --- p.3-1 / Chapter 3.1 --- Introduction --- p.3-1 / Chapter 3.2 --- Design Example 1 : Bit-serial matrix multiplier --- p.3-3 / Chapter 3.2.1 --- DCVSL design --- p.3-4 / Chapter 3.2.2 --- Micropipeline design --- p.3-4 / Chapter 3.2.3 --- The first test chip --- p.3-5 / Chapter 3.2.4 --- Second test chip --- p.3-7 / Chapter 3.3 --- Design Example 2 - Modified Booth's Multiplier --- p.3-9 / Chapter 3.3.1 --- Circuit Design --- p.3-10 / Chapter 3.3.2 --- Simulation result --- p.3-12 / Chapter 3.3.3 --- The third test chip --- p.3-14 / Chapter 4. --- Current-Sensing Completion Detection --- p.4-1 / Chapter 4.1 --- Introduction --- p.4-1 / Chapter 4.2 --- Current-sensor --- p.4-2 / Chapter 4.2.1 --- Constant current source --- p.4-2 / Chapter 4.2.2 --- Current mirror --- p.4-4 / Chapter 4.2.3 --- Current comparator --- p.4-5 / Chapter 4.3 --- Self-timed logic using CSCD --- p.4-9 / Chapter 4.4 --- CSCD test chips and testing results --- p.4-10 / Chapter 4.4.1 --- Test result --- p.4-11 / Chapter 5. --- Self-timed ICT processor architecture --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Comparison of different architecture --- p.5-3 / Chapter 5.2.1 --- General purpose Digital Signal Processor --- p.5-5 / Chapter 5.2.1.1 --- Hardware and speed estimation : --- p.5-6 / Chapter 5.2.2 --- Micropipeline without fast algorithm --- p.5-7 / Chapter 5.2.2.1 --- Hardware and speed estimation : --- p.5-8 / Chapter 5.2.3 --- Micropipeline with fast algorithm (I) --- p.5-8 / Chapter 5.2.3.1 --- Hardware and speed estimation : --- p.5-9 / Chapter 5.2.4 --- Micropipeline with fast algorithm (II) --- p.5-10 / Chapter 5.2.4.1 --- Hardware and speed estimation : --- p.5-11 / Chapter 6. --- Implementation of self-timed ICT processor --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Implementation of Self-timed 2-D ICT processor (First version) --- p.6-3 / Chapter 6.2.1 --- 1-D ICT module --- p.6-4 / Chapter 6.2.2 --- Self-timed Transpose memory --- p.6-5 / Chapter 6.2.3 --- Layout Design --- p.6-8 / Chapter 6.3 --- Implementation of Self-timed 1-D ICT processor with fast algorithm (final version) --- p.6-9 / Chapter 6.3.1 --- I/O buffers and control units --- p.6-10 / Chapter 6.3.1.1 --- Input control --- p.6-11 / Chapter 6.3.1.2 --- Output control --- p.6-12 / Chapter 6.3.1.2.1 --- Self-timed Computational Block --- p.6-13 / Chapter 6.3.1.3 --- Handshake Control Unit --- p.6-14 / Chapter 6.3.1.4 --- Integer Execution Unit (IEU) --- p.6-18 / Chapter 6.3.1.5 --- Program memory and Instruction decoder --- p.6-20 / Chapter 6.3.2 --- Layout Design --- p.6-21 / Chapter 6.4 --- Specifications of the final version self-timed ICT chip --- p.6-22 / Chapter 7. --- Testing of Self-timed ICT processor --- p.7-1 / Chapter 7.1 --- Introduction --- p.7-1 / Chapter 7.2 --- Pin assignment of Self-timed 1 -D ICT chip --- p.7-2 / Chapter 7.3 --- Simulation --- p.7-3 / Chapter 7.4 --- Testing of Self-timed 1-D ICT processor --- p.7-5 / Chapter 7.4.1 --- Functional test --- p.7-5 / Chapter 7.4.1.1 --- Testing environment and results --- p.7-5 / Chapter 7.4.2 --- Transient Characteristics --- p.7-7 / Chapter 7.4.3 --- Comments on speed and power --- p.7-10 / Chapter 7.4.4 --- Determination of optimum delay control voltage --- p.7-12 / Chapter 7.5 --- Testing of delay element and other logic cells --- p.7-13 / Chapter 8. --- Conclusions --- p.8-1 / Bibliography / Appendices
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_322710 |
| Date | January 1997 |
| Contributors | Pang, Johnson Tin-Chak., Chinese University of Hong Kong Graduate School. Division of Electronic Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, 1 v. (various pagings) : ill. (some col.) ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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