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Gate level transistor sizing by nonlinear optimization.

Thesis (M. Sc.)--Carleton University, 1992. / Includes bibliographical references. Also available in electronic format on the Internet.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/290414862
Date January 1992
CreatorsChow, Raymond W. L. Carleton University. Dissertation. Information and Systems Science.
PublisherOttawa,
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceProQuest Full Text

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